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Virtex-5 SXT

所属分类:
Virtex-5 FPGA
目标应用:
视频处理
医疗图像
手持软件无线电设备

产品参数

描述

Virtex®-5 SXT FPGA针对DSP和存储器密集型应用进行了优化,是世界上首款采用1.0V三栅极氧化层工艺技术制造而成的65nm系列的引脚兼容成员。针对具有低功耗串行连接功能的DSP和存储器密集型应用进行了优化,整合了增强型DSP模块,可以实现并行处理、最高的存储器-逻辑比和用于实现最高I/O带宽的低功耗串行收发器。
Virtex-5 SXT平台为无线WIMAX以及监控和广播等高分辨率视频等领域中的高性能数字信号处理应用提供了最高的DSP模块和逻辑资源比。增强的DSP逻辑片(DSP48E)包括一个25x18位乘法器、一个48位第二级累加和算法运算单元以及一个可扩展到96位的48位输出。更宽的数据路径和输出可支持更广泛的动态范围和更高的精度,同时 还优化了对单精度浮点运算的支持,而所消耗的资源只有90nm FPGA的一半。

特性

  • High-performance signal processing applications with advanced serial connectivity
    Cross-platform compatibility
       [1] SXT devices are footprint compatible in the same package using adjustable voltage regulators
    Most advanced, high-performance, optimal-utilization, FPGA fabric
       [2] Real 6-input look-up table (LUT) technology
       [3] Dual 5-LUT option
       [4] Improved reduced-hop routing
       [5] 64-bit distributed RAM option
       [6] SRL32/Dual SRL16 option
    Powerful clock management tile (CMT) clocking
       [1] Digital Clock Manager (DCM) blocks for zero delay mbuffering, frequency synthesis, and clock phase shifting
       [2] PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
    36-Kbit block RAM/FIFOs
       [1] True dual-port RAM blocks
       [2] Enhanced optional programmable FIFO logic Programmable
       [3] True dual-port widths up to x36
       [4] Simple dual-port widths up to x72
       [5] Built-in optional error-correction circuitry
       [6] Optionally program each block as two independent 18-Kbit blocks
    High-performance parallel SelectIO technology
       [1] 1.2 to 3.3V I/O Operation
       [2] Source-synchronous interfacing using ChipSync™ technology
       [3] Digitally-controlled impedance (DCI) active termination
       [4] Flexible fine-grained I/O banking
       [5] High-speed memory interface support
    Advanced DSP48E slices
       [1] 25 x 18, two’s complement, multiplication
       [2] Optional adder, subtracter, and accumulator
       [3] Optional pipelining
       [4] Optional bitwise logical functionality
       [5] Dedicated cascade connections
    Flexible configuration options
       [1] SPI and Parallel FLASH interface
       [2] Multi-bitstream support with dedicated fallback reconfiguration logic
       [3] Auto bus width detection capability
    System Monitoring capability on all devices
       [1] On-chip/Off-chip thermal monitoring
       [2] On-chip/Off-chip power supply monitoring
       [3] JTAG access to all monitored quantities
    Integrated Endpoint blocks for PCI Express Designs
       [1] Compliant with the PCI Express Base Specification 1.1
       [2] x1, x4, or x8 lane support per block
       [3] Works in conjunction with RocketIO™ transceivers
    Tri-mode 10/100/1000 Mb/s Ethernet MACs
    RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
    RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
    65-nm copper CMOS process technology
    1.0V core voltage
    High signal-integrity flip-chip packaging available in standard or Pb-free package options
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