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Virtex-5 TXT

Virtex-5 FPGA



Virtex®-5 TXT FPGA平台是赛灵思最新的创新成果,此平台提供一种低风险的路径,使电信设备制造商可以快速开发能适应迅速发展的100G网络市场的新产品原型,并快速将产品投入生产。这些FPGA是为数据中心中的布线器、交换机和高密度端口构建高吞吐量(40Gbps、100Gbps以上)线卡的理想选择。其高带宽功能也能满足视频广播和编辑设备、医疗影像系统及其他必须传输大量未经压缩的视频数据的应用的要求。


  • High-performance systems with double density advanced serial connectivity
    Most advanced, high-performance, optimal-utilization,FPGA fabric
       [1] Real 6-input look-up table (LUT) technology
       [2] Dual 5-LUT option
       [3] Improved reduced-hop routing
       [4] 64-bit distributed RAM option
       [5] SRL32/Dual SRL16 option
    Powerful clock management tile (CMT) clocking
       [1] Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting
       [2] PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
    36-Kbit block RAM/FIFOs
       [1] True dual-port RAM blocks
       [2] Enhanced optional programmable FIFO logic
       [3] Programmable
       [4] Built-in optional error-correction circuitry
       [5] Optionally program each block as two independent 18-Kbit blocks
    High-performance parallel SelectIO technology
       [1] 1.2 to 3.3V I/O Operation
       [2] Source-synchronous interfacing using ChipSync™ technology
       [3] Digitally-controlled impedance (DCI) active termination
       [4] Flexible fine-grained I/O banking
       [5] High-speed memory interface support
    Advanced DSP48E slices
       [1] 25 x 18, two’s complement, multiplication
       [2] Optional adder, subtracter, and accumulator
       [3] Optional pipelining
       [4] Optional bitwise logical functionality
       [5] Dedicated cascade connections
    Flexible configuration options
       [1] SPI and Parallel FLASH interface
       [2] Multi-bitstream support with dedicated fallback reconfiguration logic
       [3] Auto bus width detection capability
    System Monitoring capability on all devices
       [1] On-chip/Off-chip thermal monitoring
       [2] On-chip/Off-chip power supply monitoring
       [3] JTAG access to all monitored quantities
    Integrated Endpoint blocks for PCI Express Designs
       [1] Compliant with the PCI Express Base Specification 1.1
       [2] x1, x4, or x8 lane support per block
       [3] Works in conjunction with RocketIO™ transceivers
    Tri-mode 10/100/1000 Mb/s Ethernet MACs
    65-nm copper CMOS process technology
    1.0V core voltage
    High signal-integrity flip-chip packaging available in standard or Pb-free package options
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