Welcome Cogobuy!

厂商介绍

Cadence

  • 成立时间1988
  • 总部位于美国加州圣何塞
  • 现拥有员工约4800
  • 股票代码CDNS(纳斯达克),市值31.7亿美元

一、我们提供以下主打产品系列

  • Allegro PCB
  • OrCAD PCB

二、你知道吗?

  • 全球知名半导体与电子系统公司均将Cadence软件作为其设计标准
  • 自1991年以来,Cadence已连续在国际EDA市场中销售业绩稳居第一

三、应用领域

  • 服务于全球2万亿电子市场,包括超过3000亿的半导体市场

产品列表

型号
产品描述
RoHS
文档
 
An enterprise-class IC planning and IP reuse environment designed for larger, global organizations needing the utmost in technical and economic estimation accuracy.? Provides support for estimation with custom IP and manufacturing processes. Features a comprehensive IP reuse management system.
Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and cost.? Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance technical and economic goals.
将低功耗技术流程组成一个有机的系统,并优化其具体应用于。从而通过完整的前端到后端方法学,最佳的实践,检测表和参考流程来消除低功耗设计的风险。
Automates the validation and refinement of constraints to ensure that timing constraints are valid throughout the entire design process. Identifies issues with clock-domain crossings early in the design process, helping designers achieve convergence on design goals.
Combines automatic ECO analysis, ECO logic optimization, and design netlist modification with the industry’s most trusted equivalence checking solution. Brings greater automation, predictability, and design convergence to pre- and post-mask ECOs.
Handles large, complex datapaths, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs semantic and RTL linting checks.
Enables the creation and validation of power intent in context of the design. Combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.
Minimizes test development and production costs. Delivers a flexible compression solution plus an integrated, power-aware methodology for specifying, inserting, and verifying full-chip production tests.
Allows engineers to concurrently optimize timing, area, power, and signal integrity intent. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation capability.
Enables logic designers to account for physical interconnect—-without the need to learn how to do physical design.
Serves both front-end logic designers looking for high-quality static timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff.
Automatically generates power- and timing-aware test patterns for small delay defects. Provides defect-based modeling capability with patented pattern fault technology, the basis for gate-exhaustive coverage. Supports stuck-at and transition fault models.
Drives verification closure using incrementally developed assertion and test list plans. Captures and quickly prioritizes failures.
Supports full multi-language simulation including SystemVerilog. Provides comprehensive coverage (code, functional, transactional) and HDL analysis capabilities.
自动化和指导日常验证任务和结果的可视化。
在验证环境可用之前,通过基于断言的验证进行形式化分析,检查RTL模块设计,来加速设计的收敛
支持先进的测试平台,事务级的高层次的测试平台,基于断言的形式,模拟和加速模块级验证IP,以及仿真和在线仿真验证。包含多种复杂协议(PCI Express,AMBA,USB,OCP,以太网等)。 兼容OVM并支持各种IEEE标准语言。
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