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厂商介绍

Cadence

  • 成立时间1988
  • 总部位于美国加州圣何塞
  • 现拥有员工约4800
  • 股票代码CDNS(纳斯达克),市值31.7亿美元

一、我们提供以下主打产品系列

  • Allegro PCB
  • OrCAD PCB

二、你知道吗?

  • 全球知名半导体与电子系统公司均将Cadence软件作为其设计标准
  • 自1991年以来,Cadence已连续在国际EDA市场中销售业绩稳居第一

三、应用领域

  • 服务于全球2万亿电子市场,包括超过3000亿的半导体市场

产品列表

型号
产品描述
RoHS
文档
 
设计规则检测与版图和逻辑设计一致性检测,为SoC设计提供高良率的定制IP。
使用基于3D空间的方法进行建模、分析并优化版图,使其满足电气约束,制造规则等等。
通过基于模型的CMP热点识别与面向CMP的RC抽取,增强设计性能与良率。
根据真实光刻轮廓线来抽取器件和连线的电气参数。分析并且修复由于系统性变量产生的时序和漏电流热点。
识别并修正光刻图形的热点。使用基于模型的技术快速并且准确地预测芯片的光刻轮廓,改进参数良率和芯片性能。
在一种解决方案中提供从前端到后端设计,实现并且签收的整个流程。加快设计规则检测和版图与逻辑设计一致性验证的周期。
快速并且准确的对整个芯片进行抽取和分析。加速时序收敛并实现高质量的芯片。
Offers the performance and capacity to handle designs with growing complexity and increasing digital and analog/mixed-signal content.
无论是针对giga-gate/GHz、低功耗还是混合信号设计,无论是主流工艺节点还是先进工艺节点,都提供一个完整的单一设计平台并支持多CPU的解决方案。
Delivers scalable performance and capacity at full Spectre-level accuracy across a broad range of complex analog, RF, and mixed-signal blocks and subsystems.
Provides an advanced mixed-signal simulation solution for design and verification of analog, RF, memory, and mixed-signal SoCs.
Provides a comprehensive array of capabilities for electrical and statistical analysis, verification, and optimization of analog/mixed-signal designs, including the interfaces to many industry-standard simulators.
Performs automated and interactive block and chip authoring for custom-digital, mixed-signal, and analog designs—at any level of the hierarchy.
Accurately assess both physical and electrical variability to ensure the manufacturability of custom and mixed-signal designs, libraries, and IP.
针对电路驱动的混合信号设计,其中一小模块数字实现,提供一个完整的综合,布局布线的系统工具。
Offers rapid physical layout migration, including support for complex design rules at advanced nodes.
Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.
Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.
Enables custom design teams to efficiently analyze power and signal integrity for all designs implemented using a custom methodology.
Provides a complete design and constraint composition environment for front-to-back analog, custom-digital, RF, and mixed-signal designs.
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