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厂商介绍

Cadence

  • 成立时间1988
  • 总部位于美国加州圣何塞
  • 现拥有员工约4800
  • 股票代码CDNS(纳斯达克),市值31.7亿美元

一、我们提供以下主打产品系列

  • Allegro PCB
  • OrCAD PCB

二、你知道吗?

  • 全球知名半导体与电子系统公司均将Cadence软件作为其设计标准
  • 自1991年以来,Cadence已连续在国际EDA市场中销售业绩稳居第一

三、应用领域

  • 服务于全球2万亿电子市场,包括超过3000亿的半导体市场

产品列表

型号
产品描述
RoHS
文档
 
Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.
Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.
Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.
Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.
Enables experimentation at the initial design stages for maximum functional density and performance. Evaluates tradeoffs and provides co-design optimization of IC I/O padring/array. Optimized for co-design with Encounter Digital Implementation System.
Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.
Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.
Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substrates. Supports package substrate-level passive structures based on Pcell technology. Also enables chip-package co-design with Virtuoso.
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