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Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.
Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.
Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.
Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.
Enables experimentation at the initial design stages for maximum functional density and performance. Evaluates tradeoffs and provides co-design optimization of IC I/O padring/array. Optimized for co-design with Encounter Digital Implementation System.
Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.
Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.
Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substrates. Supports package substrate-level passive structures based on Pcell technology. Also enables chip-package co-design with Virtuoso.
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