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Virtex-5 FXT

所属分类:
Virtex-5 FPGA
目标应用:
有线和无线通信
音视频广播设备
军事
航天航空
工业系统

产品参数

描述

The Virtex™-5 FXT FPGA. Comprising the fourth platform in the 65-nanometer Virtex-5 family, Virtex-5 FXT devices combine flexibility with very high-performance embedded processing,digital signal processing and connectivity capabilities into a single chip to reduce total systemcost, power, and board real estate.

特性

  • High-performance embedded systems with advanced serial connectivity
    Cross-platform compatibility
    Most advanced, high-performance, optimal-utilization,FPGA fabric
       [1] Real 6-input look-up table (LUT) technology
       [2] Dual 5-LUT option
       [3] Improved reduced-hop routing
       [4] 64-bit distributed RAM option
       [5] SRL32/Dual SRL16 option
    Powerful clock management tile (CMT) clocking
       [1] Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting
       [2] PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
    36-Kbit block RAM/FIFOs
       [1] True dual-port RAM blocks
       [2] Enhanced optional programmable FIFO logic Programmable
       [3] Built-in optional error-correction circuitry
       [4] Optionally program each block as two independent 18-Kbit blocks
    High-performance parallel SelectIO technology
       [1] 1.2 to 3.3V I/O Operation
       [2] Source-synchronous interfacing using ChipSync™ technology
       [3] Digitally-controlled impedance (DCI) active termination
       [4] Flexible fine-grained I/O banking
       [5] High-speed memory interface support
    Advanced DSP48E slices
       [1] 25 x 18, two’s complement, multiplication
       [2] Optional adder, subtracter, and accumulator
       [3] Optional pipelining
       [4] Optional bitwise logical functionality
       [5] Dedicated cascade connections
    Flexible configuration options
       [1] SPI and Parallel FLASH interface
       [2] Multi-bitstream support with dedicated fallback reconfiguration logic
       [3] Auto bus width detection capability
    System Monitoring capability on all devices
       [1] On-chip/Off-chip thermal monitoring
       [2] On-chip/Off-chip power supply monitoring
       [3] JTAG access to all monitored quantities
    Integrated Endpoint blocks for PCI Express Designs
       [1] Compliant with the PCI Express Base Specification 1.1
       [2] x1, x4, or x8 lane support per block
       [3] Works in conjunction with RocketIO™ transceivers
    Tri-mode 10/100/1000 Mb/s Ethernet MACs
    PowerPC 440 Microprocessors
       [1] RISC architecture
       [2] 7-stage pipeline
       [3] 32-Kbyte instruction and data caches included
       [4] Optimized processor interface structure (crossbar)
    65-nm copper CMOS process technology
    1.0V core voltage
    High signal-integrity flip-chip packaging available in standard or Pb-free package options
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