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Virtex-5 LX

Virtex-5 LX
所属分类
Virtex
目标应用
医学图像处理视频处理

The Xilinx® Virtex-5 LX Platform consists of six devices offering up to 330,000 logic cells, 1200 user I/Os, 10-Mbits of 36-Kbit block RAM, and 3.2-Mbits of distributed RAM, plus an abundance of hardened intellectual property (IP) blocks.
Based on the revolutionary new 65-nm ExpressFabric™ technology, the new Virtex-5 LX devices allow designs to be packed more efficiently, thus improving performance and utilization while reducing power consumption. Virtex-5 LX FPGAs deliver 30 percent higher performance, consume 45 percent less area and provide the industry’s lowest dynamic power – 35 percent lower than previous generation 90-nm FPGAs. The Virtex-5 LX family also features 550 MHz clocking technology with performance-tuned IP blocks. High-performance SelectIO™ features provide the fastest connection possible to external memory such as 667 Mbps DDR2 SDRAM and 1200 Mbps QDR II SRAM.

High-performance general logic applications
Most advanced, high-performance, optimal-utilization,FPGA fabric
   [1] Real 6-input look-up table (LUT) technology
   [2] Dual 5-LUT option
   [3] Improved reduced-hop routing
   [4] 64-bit distributed RAM option
   [5] SRL32/Dual SRL16 option.
Powerful clock management tile (CMT) clocking
   [1] Digital Clock Manager (DCM) blocks for zero delay
   [2] buffering, frequency synthesis, and clock phase shifting
   [3] PLL blocks for input jitter filtering, zero delay buffering,
   [4] frequency synthesis, and phase-matched clock division
36-Kbit block RAM/FIFOs
   [1] True dual-port RAM blocks
   [2] Enhanced optional programmable FIFO logic
   [3] Programmable
   [4] Built-in optional error-correction circuitry
   [5] Optionally program each block as two independent 18-Kbit
High-performance parallel SelectIO technology
   [1] 1.2 to 3.3V I/O Operation
   [2] Source-synchronous interfacing using ChipSync™ technology
   [3] Digitally-controlled impedance (DCI) active termination
   [4] Flexible fine-grained I/O banking
   [5] High-speed memory interface support
Advanced DSP48E slices
   [1] 25 x 18, two’s complement, multiplication
   [2] Optional adder, subtracter, and accumulator
   [3] Optional pipelining
   [4] Optional bitwise logical functionality
   [5] Dedicated cascade connections
Flexible configuration options
   [1] SPI and Parallel FLASH interface
   [2] Multi-bitstream support with dedicated fallback
   [3] reconfiguration logic
   [4] Auto bus width detection capability
System Monitoring capability on all devices
   [1] On-chip/Off-chip thermal monitoring
   [2] On-chip/Off-chip power supply monitoring
   [3] JTAG access to all monitored quantities
65-nm copper CMOS process technology
1.0V core voltage
High signal-integrity flip-chip packaging available in standard or Pb-free package options

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