Welcome Cogobuy!



  • 成立时间1988
  • 总部位于美国加州圣何塞
  • 现拥有员工约4800
  • 股票代码CDNS(纳斯达克),市值31.7亿美元


  • Allegro PCB


  • 全球知名半导体与电子系统公司均将Cadence软件作为其设计标准
  • 自1991年以来,Cadence已连续在国际EDA市场中销售业绩稳居第一


  • 服务于全球2万亿电子市场,包括超过3000亿的半导体市场


Delivers advanced simulation capabilities for analog/mixed-signal development. Provides design entry feedback, component modeling, stress analysis, and yield projections.
Provides a multi-style logic authoring-driven, constraint-driven flow. Manages design constraints, net classes, buses, extended nets, and differential pairs.
Enables rapid, intuitive schematic editing and hierarchical design with optimized sharing and reuse of components and subassemblies. Automates integration of field programmable gate arrays (FPGAs) and programmable logic devices (PLDs).
Converts Allegro Design Authoring schematics and Allegro PCB Designer PCBs to content-rich PDFs?creating a secure, single-file representation of the design.
Provides a collaborative environment that integrates design tools, library development and distribution, data management, and process control?all aimed at increasing productivity, reducing errors, and eliminating redundancy.
The Allegro FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for one or more FPGAs.? It also allows users to optimize pin assignment after placement or during routing of signals on the PCB.?
Speeds designs from placement and routing through to manufacturing with powerful features such as design partitioning, RF design capabilities, and interconnect design planning. Production-proven to increase productivity and help engineers quickly ramp up to volume production.
Significantly accelerates creation and validation of schematic, PCB footprint and digital simulation map files. This enables librarians, engineers and/or designers to reduce development time for high-pin-count devices from days to minutes.
Provides advanced interconnect modeling for constraint development and electrical analysis of multi-gigabit designs. Simulates high-speed signals, systems, and power delivery networks at the single- or multi-board level.
Offers full-featured schematic editing of complex designs through hierarchical and variant design capabilities for fast, intuitive design capture. Robust component information system (CIS) promotes use of preferred, current parts to accelerate design capture and reduce project costs.
The OrCAD FPGA System Planner offers technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for an FPGA.
Offers a proven, scalable, easy-to-use PCB editing and routing solution. Delivers a comprehensive feature set and seamless PCB design environment to take designs from concept to production.
Provides detailed interconnect modeling and electrical analysis. Enables pre- and post-layout signal integrity analysis at any stage.
Simulates analog/mixed-signal circuits quickly and completely to improve productivity and data integrity. Advanced Analysis prevents board failures by determining which components are over-stressed using Smoke analysis or by observing component yields using Monte Carlo analysis.
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