Welcome Cogobuy!

An enterprise-class IC planning and IP reuse environment designed for larger, global organizations needing the utmost in technical and economic estimation accuracy.? Provides support for estimation with custom IP and manufacturing processes. Features a comprehensive IP reuse management system.
Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and cost.? Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance technical and economic goals.
Automates the validation and refinement of constraints to ensure that timing constraints are valid throughout the entire design process. Identifies issues with clock-domain crossings early in the design process, helping designers achieve convergence on design goals.
Combines automatic ECO analysis, ECO logic optimization, and design netlist modification with the industry’s most trusted equivalence checking solution. Brings greater automation, predictability, and design convergence to pre- and post-mask ECOs.
Handles large, complex datapaths, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs semantic and RTL linting checks.
Enables the creation and validation of power intent in context of the design. Combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.
Minimizes test development and production costs. Delivers a flexible compression solution plus an integrated, power-aware methodology for specifying, inserting, and verifying full-chip production tests.
Allows engineers to concurrently optimize timing, area, power, and signal integrity intent. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation capability.
Enables logic designers to account for physical interconnect—-without the need to learn how to do physical design.
Serves both front-end logic designers looking for high-quality static timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff.
Automatically generates power- and timing-aware test patterns for small delay defects. Provides defect-based modeling capability with patented pattern fault technology, the basis for gate-exhaustive coverage. Supports stuck-at and transition fault models.
Drives verification closure using incrementally developed assertion and test list plans. Captures and quickly prioritizes failures.
Supports full multi-language simulation including SystemVerilog. Provides comprehensive coverage (code, functional, transactional) and HDL analysis capabilities.
支持先进的测试平台,事务级的高层次的测试平台,基于断言的形式,模拟和加速模块级验证IP,以及仿真和在线仿真验证。包含多种复杂协议(PCI Express,AMBA,USB,OCP,以太网等)。 兼容OVM并支持各种IEEE标准语言。
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