欢迎光临科通芯城!

科通芯城,IC及其他电子元器件交易型电商平台100%正品保证!

AT80574JJ053N

AT80574JJ053N

  • 品牌:Intel
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:Intel? Xeon? Processor L5410 (12M Cache, 2.33 GHz, 1333 MHz FSB)
  • 封装:--
  • 类别:至强处理器
参数 数值
# of Cores 4
# of Processing Die Transistors 820 million
# of Threads 4
Bus/Core Ratio 7
Clock Speed 2.33 GHz
Embedded Options Available Yes
Enhanced Intel SpeedStep® Technology Yes
Execute Disable Bit Yes
FSB Parity Yes
FSB Speed 1333 MHz
Idle States Yes
Instruction Set 64-bit
Intel® 64 Yes
Intel® Demand Based Switching Yes
Intel® Hyper-Threading Technology No
Intel® Trusted Execution Technology No
Intel® Turbo Boost Technology No
Intel® Virtualization Technology (VT-x) Yes
Intel® VT-x with Extended Page Tables (EPT) Yes
L2 Cache 12 MB
Launch Date Q1'08
Lithography 45 nm
Low Halogen Options Available See MDDS
Max TDP 50 W
Package Size 37.5mm x 37.5mm
Processing Die Size 214 mm 2
Processor Number L5410
Recommended Customer Price TRAY: $323 BOX : $351
Sockets Supported LGA771
Status Launched
Supplemental SKU No
T CASE 57°C
VID Voltage Range 0.850V-1.3500V


这些基于四核、双核及单核英特尔® 至强® 处理器的平台采用 45 纳米和 65 纳米制程技术;拥有出色的性能、能效和极长的生命周期支持,是进行密集计算的存储与通信应用的理想选择。


  • 英特尔® 虚拟化技术: 允许硬件平台作为多个虚拟平台。
  • Intel® 64 架构: 支持 64 位指令。
  • 多核选项: 提高应对多线程应用的性能
  • 英特尔® SSE4 指令: 47 条新指令用以提高应对媒体与高性能计算应用的性能。

交互式结构图



应用注释
序号 PDF 描述
1 White Paper: Interfacing I²C Devices to Intel's SMBus Controller White Paper: Interfacing I²C Devices to Intel's SMBus Controller
2 White Paper: Extending the World’s Most Popular Processor Architecture White Paper: Extending the World’s Most Popular Processor Architecture
3 White Paper: Optimizing Embedded System Performance—Impact of Data Prefetching on a Medical Imaging White Paper: Optimizing Embedded System Performance—Impact of Data Prefetching on a Medical Imaging Application
4 White Paper: Introducing the 45nm Next-Generation Intel® Core Microarchitecture White Paper: Introducing the 45nm Next-Generation Intel® Core Microarchitecture
5 White Paper: Programming Models for Packet Processing Applications on Multi-Core Intel® Architecture White Paper: Programming Models for Packet Processing Applications on Multi-Core Intel® Architecture Systems
6 White Paper: PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Cons White Paper: PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Considerations
7 White Paper: Thermal Guidance for AdvancedTCA Designs White Paper: Thermal Guidance for AdvancedTCA Designs
8 White Paper: Consolidating Communications and Networking Workloads onto One Architecture White Paper: Consolidating Communications and Networking Workloads onto One Architecture
9 White Paper: JTAG 101 White Paper: JTAG 101
10 White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets
11 White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on I White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on Intel® Architecture
12 White Paper: Upgrading to Multi-Core Ecosystem Keeps Car Simulator Running in the Fast Lane White Paper: Upgrading to Multi-Core Ecosystem Keeps Car Simulator Running in the Fast Lane
13 White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts
14 White Paper: Designing Systems without a Suspend Supply White Paper: Designing Systems without a Suspend Supply
15 White Paper: Asymmetric Multi-Processing, Embedded and Communication MC Usage Model White Paper: Asymmetric Multi-Processing, Embedded and Communication MC Usage Model
16 Application Note: Alcatel-Lucent Converged IP Messaging Solution Application Note: Alcatel-Lucent Converged IP Messaging Solution
17 White Paper: Platform-Level error Handling Strategies for Intel® Systems White Paper: Platform-Level error Handling Strategies for Intel® Systems
18 White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms
19 White Paper: Seven Tips to Get Started on Embedded Multi-Core White Paper: Seven Tips to Get Started on Embedded Multi-Core
20 Application Note: AP-485 Intel® Processor Identification and CPUID Instruction Application Note: AP-485 Intel® Processor Identification and CPUID Instruction
21 White Paper: What Does It Mean to Be I/O Bound? White Paper: What Does It Mean to Be I/O Bound?
22 White Paper: Choosing the Right Storage Solution for Your Embedded Application White Paper: Choosing the Right Storage Solution for Your Embedded Application
23 White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles
24 White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines
25 Application Note: Designing Embedded Systems for Testability Application Note: Designing Embedded Systems for Testability
26 Case Study: Migrating the Ericsson* Operations Support System: RISC or Intel® based Servers Case Study: Migrating the Ericsson* Operations Support System: RISC or Intel® based Servers
设计计算器和清单
序号 PDF 描述
1 Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0
2 Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1
3 Design Guide: 603-Pin Socket Design Guide: 603-Pin Socket
4 Design Guide: ITP700 Debug Port Design Guide: ITP700 Debug Port
5 Design Guide: LGA771 Socket Design Guide: LGA771 Socket
6 Design Guide: Voltage Regulator Module (VRM) 9.0 DC-DC Converter Design Guide: Voltage Regulator Module (VRM) 9.0 DC-DC Converter
散热和机械
序号 PDF 描述
1 Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor L5408 Series in Embedded Applications Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor L5408 Series in Embedded Applications
2 Thermal & Mechanical Design Guidelines: Quad-Core Intel® Xeon® Processor 5400 Series Thermal & Mechanical Design Guidelines: Quad-Core Intel® Xeon® Processor 5400 Series
3 White Paper: Thermal Design Considerations for Embedded Applications White Paper: Thermal Design Considerations for Embedded Applications
4 Thermal & Mechanical Design Guide: Intel® 5100 Memory Controller Hub Chipset Thermal & Mechanical Design Guide: Intel® 5100 Memory Controller Hub Chipset
5 Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor 5200 Series Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor 5200 Series
6 Power Profiling for Embedded Applications Power Profiling for Embedded Applications
7 Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor 5200 Series in Embedded Applications Thermal & Mechanical Design Guidelines: Intel® Xeon® Processor 5200 Series in Embedded Applications
数据表和规格更新
序号 PDF 描述
1 Datasheet: Intel® I/O Controller Hub 9 (ICH9) Family Datasheet: Intel® I/O Controller Hub 9 (ICH9) Family
2 Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller
3 Specification Update: Intel® 82576 Gigabit Ethernet Controller Specification Update: Intel® 82576 Gigabit Ethernet Controller
4 Specification Update: Intel® Xeon® Processor 5200 Series Specification Update: Intel® Xeon® Processor 5200 Series
5 Specification Update: Quad-Core Intel® Xeon® Processor 5400 Series Specification Update: Quad-Core Intel® Xeon® Processor 5400 Series
6 Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller
7 Datasheet: Quad-Core Intel® Xeon® Processor 5400 Series Datasheet: Quad-Core Intel® Xeon® Processor 5400 Series
8 DB400/800 Differential Clock Buffer Specification DB400/800 Differential Clock Buffer Specification
9 Specification Update: Intel® 5100 Memory Controller Hub (MCH) Chipset Specification Update Specification Update: Intel® 5100 Memory Controller Hub (MCH) Chipset Specification Update
10 Datasheet: Intel® 5100 Memory Controller Hub Datasheet: Intel® 5100 Memory Controller Hub
产品简介
序号 PDF 描述
1 Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity) Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity)
2 Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller H Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller Hub Chipset
3 Product Brief: Intel® 5100 Memory Controller Hub Chipset for Embedded Computing Product Brief: Intel® 5100 Memory Controller Hub Chipset for Embedded Computing
4 Product Brief: Intel® 82576 Gigabit Ethernet Controller Product Brief: Intel® 82576 Gigabit Ethernet Controller
5 产品简介: 45 纳米英特尔® 至强® 处理器 5400/5200 系列 产品简介: 45 纳米英特尔® 至强® 处理器 5400/5200 系列
以太网控制器
序号 PDF 描述
1 Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity) Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity)
2 Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller
3 Specification Update: Intel® 82576 Gigabit Ethernet Controller Specification Update: Intel® 82576 Gigabit Ethernet Controller
4 Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller
5 Product Brief: Intel® 82576 Gigabit Ethernet Controller Product Brief: Intel® 82576 Gigabit Ethernet Controller
开发主板和套件
序号 PDF 描述
1 Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller H Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller Hub Chipset
2 开发套件: 四核和双核英特尔®至强®处理器5000系列和 英特尔®5100内存控制器芯片组开发套件 开发套件: 四核和双核英特尔®至强®处理器5000系列和 英特尔®5100内存控制器芯片组开发套件
示意图和规划文件
序号 PDF 描述
1 Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller H Development Kit User Guide: Intel® Xeon® Processor 5000 Sequence and Intel® 5100 Memory Controller Hub Chipset
性能指标评测
序号 PDF 描述
1 White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on I White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on Intel® Architecture
2 White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization
3 White Paper: Hardware Level I/O Benchmarking of PCI Express on Intel® Platforms White Paper: Hardware Level I/O Benchmarking of PCI Express on Intel® Platforms
平台概述
序号 PDF 描述
1 Intel® 5100 MCH Chipset Launch Presentation Intel® 5100 MCH Chipset Launch Presentation
模拟模型
序号 PDF 描述
1 Boundary Scan Description Language (BSDL): Intel® Xeon® Processor 5200 Series Boundary Scan Description Language (BSDL): Intel® Xeon® Processor 5200 Series
联系我们

联系我们

电话
+86 400 8830 393

传真
+86(755) 2674 4090

电邮
service_info@cogobuy.com

微信
芯云<cogocloud>

快速询价
快速询价
购买指引
购买指引
官方微信

官方微信

官方微信
返回顶部