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Cadence SiP Co-Design

Cadence SiP Co-Design

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.
  • 封装:--
  • 类别:IC 封装和SiP设计


The Cadence package and IC design environments are flexibly integrated to match your design style. Whether chip and package are designed by the same person or by members of different companies in different geographies, Cadence has a co-design methodology to meet your needs.

A single desktop solution is available where designers using Encounter Digital Implementation System (EDIS) and Cadence SiP Layout can exchange die pad ring information in real time allowing for rapid trade-offs that create an optimized chip-package interface. For design teams that work in different geographies (or even different companies), die abstract information can be captured in a file by EDIS or Virtuoso and sent to designers using Cadence SiP Layout for package design. Should negotiations need to take place the SiP Layout user can pass back a revised die abstract where an ECO process can be run to accept, partially accept, or reject the proposed changes in the IC design environment. This “distributed co-design” methodology has the benefit of allowing design teams that are globally dispersed to communicate design changes efficiently while allowing designers to continue using their natural design environment, whether that be on a Linux or Windows workstation.

As organizational methods of different companies tend to vary, Cadence has had the opportunity to understand a number of different approaches taken to optimize the chip-package interface. We offer our experience to you through a number of utilities that supplement the more typical flows. These utilities include RDL route exchange between the chip and package environments, language based design rule checking, and automatic bump matrix pattern generation.

This combination of flexible flows backed up by powerful support utilities has helped design teams raise their level of productivity through rapid prototyping and cost cutting exercises that had not been achievable prior to utilizing Cadence co-design technology. Half day workshops are available to jump start your co-design activities.

文档类型:

Datasheet
Datasheet
序号 PDF 描述
1 Cadence Chip-Package-Board Co-Design Solution Datasheet Cadence Chip-Package-Board Co-Design Solution Datasheet
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