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Cadence SiP Digital SI

Cadence SiP Digital SI

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.
  • 封装:--
  • 类别:IC 封装和SiP设计



Features/Benefits
  • Reads/writes Cadence SiP Layout files
  • Streamlines virtual prototyping, interconnect exploration, analysis, and modeling
  • Provides fast, high-capacity simulation for multi-gigahertz interconnect analysis
  • Performs topology editing and solution space exploration
  • Includes SPICE-based simulation
  • Provides embedded integration with partner supplied 3D field solvers
  • Provides hierarchical constraint management
  • Enables virtual substrate editing and post-layout debugging
  • Simplifies design debug and reviews with Cadence 3D Design Viewer

Conference Paper
序号 PDF 描述
1 Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs
2 Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs
Datasheet
序号 PDF 描述
1 Cadence RF Design Methodology Kit Datasheet Cadence RF Design Methodology Kit Datasheet
2 Cadence SiP Digital Design Datasheet Cadence SiP Digital Design Datasheet
Release Information
序号 PDF 描述
1 Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation
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