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Cadence SiP Layout

Cadence SiP Layout

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.
  • 封装:--
  • 类别:IC 封装和SiP设计



Cadence® SiP Layout is the physical co-design and place-and-route solution for complex 3D SiP package design. Supporting all package interconnect strategies and combinations, SiP Layout provides constraint-driven layout of the package substrate. Since it must operate in a 3D world, SiP Layout allows stack assembly optimization with 3D layout and editing. It also performs autoroute and breakout on flip-chip dies to reduce time-consuming and tedious manual breakout. Comprehensive DFM checking and modification improve substrate yield. Design review documentation and debug, followed by direct manufacturing tapeout, complete the package.

Features/Benefits
  • Provides 3D die stack creation/editing for rapid stack assembly and optimization
  • Completes I/O padring/array co-design with multi-level optimization
  • Enables connectivity assignment to minimize layer usage based on SI analysis
  • Includes solid model 3D design viewer with snapshots for design review
  • Performs 3D wirebond verification and DRC
  • Supports bi-directional ECO and LVS flow for full co-design environment profiles
  • Includes a comprehensive suite of DFM preparation technologies
  • Supports highly integrated (Encounter) and distributed (die abstract with Encounter or Virtusoso) co-design methodologies to match your chip-package design environments

文档类型:

Datasheet
Datasheet
序号 PDF 描述
1 Cadence Chip-Package-Board Co-Design Solution Datasheet Cadence Chip-Package-Board Co-Design Solution Datasheet
2 Cadence RF Design Methodology Kit Datasheet Cadence RF Design Methodology Kit Datasheet
3 Cadence SiP Digital Design Datasheet Cadence SiP Digital Design Datasheet
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