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C-to-Silicon Compiler

C-to-Silicon Compiler

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:新一代的高阶综合技术,能从有时序或无时序的C/C++/SystemC自动生成可综合的高质量的RTL代码—无论是面积还是性能上都能满足客户需求。
  • 封装:--
  • 类别:系统设计与验证



At the core of Cadence system-level design solutions, Cadence® C-to-Silicon Compiler automatically generates synthesizable RTL starting from untimed C/C++/SystemC® with as little as 10% of the effort required using manual methods. C-to-Silicon Compiler has been architected from the ground up with four unique capabilities that deliver revolutionary advantages to hardware architects and RTL designers:

  • Embedded logic synthesis (ELS) enables parallel optimization of control and datapath logic, greatly enhancing the quality of results
  • Behavior-structure-timing (BST) database enables true incremental synthesis and much faster design and verification turnaround time
  • Constraint-functionality separation (CFS) enables efficient reuse across multiple applications and process technologies
  • Fast hardware models (FHMs) accelerate verification and enable early hardware/software co-development
Features/Benefits
  • Accepts widest-range of C/C++/SystemC coding styles and constructs, including templates, classes, user-defined types, and certain types of pointers
  • Embedded Encounter® RTL Compiler delivers consistently accurate timing and area information during the entire high-level synthesis process, resulting in signoff-quality RTL for all types of designs
  • BST database tracks evolution of design-data starting from C/C++/SystemC source files all the way to physical implementation, enabling direct mapping of physical design data back to RTL as well as the original C/C++/SystemC source code
  • CFS keeps functionality, communication, and design constraints all independent, enabling designers to keep their source code “golden” and retarget new applications by only changing communication/design constraints
  • Approximately-timed FHMs generated in SystemC simulate 80-90% as fast as the original untimed input model, enabling fast verification and early hardware-software co-development
  • Interactive GUI provides a complete environment for synthesis, analysis, and debug, giving users excellent control and visibility over the high-level synthesis process

Webinar
序号 PDF 描述
1 Archived webinar - Calypto: Application of Sequential Analysis for ESL Methodology Adoption Archived webinar - Calypto: Application of Sequential Analysis for ESL Methodology Adoption
2 Archived webinar - CircuitSutra: Role of Standards in TLM Driven Design and Verification Methodology Archived webinar - CircuitSutra: Role of Standards in TLM Driven Design and Verification Methodology
3 Archived webinar - Magillem: Role of IP-XACT in TLM Archived webinar - Magillem: Role of IP-XACT in TLM
4 Archived webinar - TLM-Driven Design and Verification Solution and Methodology Archived webinar - TLM-Driven Design and Verification Solution and Methodology
5 Archived webinar - TSMC Reference Flow 11: ESL Focus on High-Level Synthesis Archived webinar - TSMC Reference Flow 11: ESL Focus on High-Level Synthesis
6 Archived webinar - TSMC Reference Flow 11: ESL Focus on TLM Design and Verification Methodology Archived webinar - TSMC Reference Flow 11: ESL Focus on TLM Design and Verification Methodology
7 Archived webinar - XtremeEDA: The Importance of a Complete Methodology for ESL Archived webinar - XtremeEDA: The Importance of a Complete Methodology for ESL
8 Practical application of high-level synthesis in SoC designs on-demand webinar Practical application of high-level synthesis in SoC designs on-demand webinar
Success Story
序号 PDF 描述
1 Cadence and Casio Success Story Cadence and Casio Success Story
2 Cadence and Renesas System Design and Verification Success Story Cadence and Renesas System Design and Verification Success Story
3 Technical University of Braunschweig and Cadence Success Story Technical University of Braunschweig and Cadence Success Story
Datasheet
序号 PDF 描述
1 Cadence C-to-Silicon Compiler Datasheet Cadence C-to-Silicon Compiler Datasheet
Technical Paper
序号 PDF 描述
1 Cadence C-to-Silicon Compiler Delivers on the Promise of High-Level Synthesis Technical Paper Cadence C-to-Silicon Compiler Delivers on the Promise of High-Level Synthesis Technical Paper
Article
序号 PDF 描述
1 Case study: High-Level Synthesis – Ready for prime-time? Case study: High-Level Synthesis – Ready for prime-time?
Demo
序号 PDF 描述
1 Next-generation High Level Synthesis: Cadence C-to-Silicon Compiler Demo Next-generation High Level Synthesis: Cadence C-to-Silicon Compiler Demo
White Paper
序号 PDF 描述
1 TLM-Driven Design and Verification – Time for a Methodology Shift White Paper TLM-Driven Design and Verification – Time for a Methodology Shift White Paper
Book
序号 PDF 描述
1 TLM-Driven Design and Verification Methodology Book TLM-Driven Design and Verification Methodology Book
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