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Encounter Conformal Constraint Designer

Encounter Conformal Constraint Designer

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:Automates the validation and refinement of constraints to ensure that timing constraints are valid throughout the entire design process. Identifies issues with clock-domain crossings early in the design process, helping designers achieve convergence on de
  • 封装:--
  • 类别:逻辑设计



Validating, and modifying the constraints necessary for design implementation has conventionally involved manual and error-prone processes, increasing the risk of bad silicon. Validating clock-domain crossings (CDCs) typically requires challenging setup and detailed knowledge of clock propagation. As an increasing number of IP blocks come together in a design, each with its own timing constraints and set of clocks, the risk of an un-verified SoC ending in silicon failure also grows. Encounter® Conformal® Constraint Designer provides the most complete and efficient path to develop and manage constraints and CDCs, ensuring they are functionally correct—from RTL to layout. By pinpointing real design issues quickly and accurately, delivering higher-quality timing constraints, and finding issues with clock domain synchronizers, it allows designers to reduce overall design cycle times and enhance quality of silicon in complex SoC designs.

Features/Benefits
  • Ensures timing constraints are correct and complete
  • Shortens design cycles with a comprehensive analysis environment that checks the creation and integration of block-level and top-level constraints
  • Validates that CDCs have proper synchronizers in place, easily visualized through a FIFO manager
  • Reduces the risk of re-spins through formal validation of constraints
  • Speeds convergence for timing closure by quickly validating failing timing paths as functionally false
  • Creates initial constraints effortlessly with the SDC Advisor

Conference Paper
序号 PDF 描述
1 Automating Functional ECOs using Encounter Conformal Technology Automating Functional ECOs using Encounter Conformal Technology
2 Functional ECO with Conformal Technology Functional ECO with Conformal Technology
3 How Not to "Wing It" on Your Timing Constraints How Not to "Wing It" on Your Timing Constraints
4 Low-Power Verification Flow to Ease the Pain of Implementing MTCMOS-based MSMV Wireless Designs Low-Power Verification Flow to Ease the Pain of Implementing MTCMOS-based MSMV Wireless Designs
5 Real Design Challenges of Low-Power Physical Implementation Real Design Challenges of Low-Power Physical Implementation
6 Static Verification for Design Reuse and Quality Static Verification for Design Reuse and Quality
Demo
序号 PDF 描述
1 Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design
Brochure
序号 PDF 描述
1 Cadence Encounter Digital IC Design Platform Brochure Cadence Encounter Digital IC Design Platform Brochure
Datasheet
序号 PDF 描述
1 Encounter Conformal Constraint Designer Datasheet Encounter Conformal Constraint Designer Datasheet
Cadence Article
序号 PDF 描述
1 Interview: Freescale's Alex Albuerne uses Encounter Timing System to Overcome Timing Challenges Interview: Freescale's Alex Albuerne uses Encounter Timing System to Overcome Timing Challenges
2 Interview: Low-Power Design and Verification using CPF Interview: Low-Power Design and Verification using CPF
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