欢迎光临科通芯城!

科通芯城,IC及其他电子元器件交易型电商平台100%正品保证!

Encounter RTL Compiler

Encounter RTL Compiler

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:Allows engineers to concurrently optimize timing, area, power, and signal integrity intent. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation capability.
  • 封装:--
  • 类别:逻辑设计



With its combination of breakthrough algorithms, efficient data structures, and modern programming techniques, Encounter RTL Compiler delivers the best speed, area, and power after physical implementation for the most challenging designs. New advanced, , global synthesis technology further improves these results while delivering even faster runtimes. At the core of Encounter RTL Compiler is a break¬through synthesis algorithm—global-focus mapping (GFM). This technique devotes more time to examining the overall solution space to deliver an optimized netlist for meeting your design intent goals throughout physical design.

Encounter RTL Compiler performs multi-objective optimization that simultaneously considers timing, power, and area intent to create logic structures that converge on all these goals in a single pass.

Features/Benefits
  • A well-balanced logic structure isolates critical paths, reduces power, area, and congestion in off-critical logic, and enables faster timing closure and design convergence through place-and-route
  • Spatial technology eliminates the need for wireload models by modeling physical interconnect at a higher level of abstraction for use in RTL-to-gate optimization
  • Encounter RTL Compiler with Physical incorporates Encounter Digital Implementation System silicon virtual prototyping technology into synthesis, providing real physical timing to logic optimi¬zation and analysis
  • Reduces power consumption through single-pass multi-Vt optimi¬zation, hierarchical and multi-stage clock gating, true top-down multi-supply voltage exploration and synthesis, and full power shutoff support with the Common Power Format (CPF)
  • Shrinks die sizes with multi-objective optimization, which creates smaller logic structures for non–timing-critical regions
  • Multi-mode synthesis optimization and analysis accelerates overall turnaround time to design closure for complex chips with multiple functional modes
  • Superthreading technology leads to superior runtimes, quicker turnaround times, and faster convergence on design goals
  • Superior capacity increases produc¬tivity by enabling chip-level synthesis and eliminating manual partitioning, budgeting, and reassembly
  • A built-in design quality analyzer identifies pre-synthesis design issues that may lead to sub-optimal or unintended results
  • Easy to adopt—uses standard inputs and outputs so that customers requiring improved quality of silicon (timing, area, and power after wires) can get en route quickly to achieving their design goals

Conference Paper
序号 PDF 描述
1 A Practical Guide to Deploying Assertions in RTL A Practical Guide to Deploying Assertions in RTL
2 HW/SW Co-Simulation HW/SW Co-Simulation
3 Low-Power Methodologies in a Multi-Core Networking Chip Low-Power Methodologies in a Multi-Core Networking Chip
4 Predicting Physical Design Results Using Advanced Synthesis Features Predicting Physical Design Results Using Advanced Synthesis Features
5 RTL Compiler Optimization on Full Chip Complex SoC design RTL Compiler Optimization on Full Chip Complex SoC design
6 Scalable RTL in Design and Verification Scalable RTL in Design and Verification
7 Speeding up HW/SW Co-Development using HW Emulation Speeding up HW/SW Co-Development using HW Emulation
8 Timing closure on a 1GHz DSP-processor using RTL Compiler and SoC Encounter Timing closure on a 1GHz DSP-processor using RTL Compiler and SoC Encounter
9 Using Configurable Memory Controller Design IP with Encounter RTL Compiler Using Configurable Memory Controller Design IP with Encounter RTL Compiler
10 Verification of Low-Power Designs using CPF Verification of Low-Power Designs using CPF
11 Verification of Low-Power Designs using CPF Verification of Low-Power Designs using CPF
Webinar
序号 PDF 描述
1 Archived webinar - How Logic Designers Can Avoid Congestion Nightmares Archived webinar - How Logic Designers Can Avoid Congestion Nightmares
Success Story
序号 PDF 描述
1 Cadence and NetEffect Success Story Cadence and NetEffect Success Story
2 Technical University of Braunschweig and Cadence Success Story Technical University of Braunschweig and Cadence Success Story
White Paper
序号 PDF 描述
1 Eliminating Routing Congestion Issues with Logic Synthesis White Paper Eliminating Routing Congestion Issues with Logic Synthesis White Paper
2 Global Synthesis for Design Closure White Paper Global Synthesis for Design Closure White Paper
Datasheet
序号 PDF 描述
1 Encounter RTL Compiler Compiler Advanced Physical Option Datasheet Encounter RTL Compiler Compiler Advanced Physical Option Datasheet
2 Encounter RTL Compiler Datasheet Encounter RTL Compiler Datasheet
Cadence Article
序号 PDF 描述
1 Learn to Optimize Your Low-Power Design Process Learn to Optimize Your Low-Power Design Process
eBook
序号 PDF 描述
1 Practical Guide to Low-Power Design - User Experience with CPF Practical Guide to Low-Power Design - User Experience with CPF
联系我们

联系我们

电话
+86 400 8830 393

传真
+86(755) 2674 4090

电邮
service_info@cogobuy.com

微信
芯云<cogocloud>

快速询价
快速询价
购买指引
购买指引
官方微信

官方微信

官方微信
返回顶部