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Incisive Design Team Manager

Incisive Design Team Manager

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:Drives verification closure using incrementally developed assertion and test list plans. Captures and quickly prioritizes failures.
  • 封装:--
  • 类别:功能验证
Cadence Article
序号 PDF 描述
1 Beyond the Compliance Checklist Beyond the Compliance Checklist
2 Do's and Dont's for Systematically Implementing Late Engineering Changes on Your Project Do's and Dont's for Systematically Implementing Late Engineering Changes on Your Project
3 Interview: Verification Planning and Management Methodology Focuses on All the Right Things Interview: Verification Planning and Management Methodology Focuses on All the Right Things
Conference Paper
序号 PDF 描述
1 Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodol Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodology
2 Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approa Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approach
3 Coverage-Driven Verification for Mixed-Signal Systems Coverage-Driven Verification for Mixed-Signal Systems
4 Implementing an Automated Checking Scheme for a Video-Processing Device Implementing an Automated Checking Scheme for a Video-Processing Device
5 Integrating Design IP and Verification IP to Ensure Quality and Predictability Integrating Design IP and Verification IP to Ensure Quality and Predictability
6 Leveraging Assertions in System Verilog Testbench to get to Closure Leveraging Assertions in System Verilog Testbench to get to Closure
7 Methods to Improve Verification Quality on the Module Level Methods to Improve Verification Quality on the Module Level
8 Methods to Improve Verification Quality on the Module Level Methods to Improve Verification Quality on the Module Level
9 Speed up and prove verification by using a generic scoreboard library Speed up and prove verification by using a generic scoreboard library
10 Test Sequence Reuse from Block to System with the Incisive Plan-to-Closure Methodology Test Sequence Reuse from Block to System with the Incisive Plan-to-Closure Methodology
Demo
序号 PDF 描述
1 Cadence Low-Power Solution Demo Cadence Low-Power Solution Demo
Technical Paper
序号 PDF 描述
1 Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf
Release Information
序号 PDF 描述
1 Interview: By Popular Demand—SystemVerilog Open Verification Methodology Interview: By Popular Demand—SystemVerilog Open Verification Methodology
Application Brief
序号 PDF 描述
1 Packaging Reusable Components, EZ-start Guide Packaging Reusable Components, EZ-start Guide
2 Working with Interfaces, EZ-start Guide Working with Interfaces, EZ-start Guide
White Paper
序号 PDF 描述
1 Power-Aware Verification Spans IC Design Cycle White Paper Power-Aware Verification Spans IC Design Cycle White Paper
eBook
序号 PDF 描述
1 Practical Guide to Low-Power Design - User Experience with CPF Practical Guide to Low-Power Design - User Experience with CPF
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