Welcome to Cogobuy!

Cogobuy, China's renowned IC and other electronic component trading platform, which guarantees 100% genuine products!

Incisive Enterprise Simulator

Incisive Enterprise Simulator

  • brand:Cadence
  • Packaging:--
  • Lead-free status/ROHS: --
  • Seller:科通芯城自营
  • Description:支持多语言,涵盖人系统级到门级的覆盖率驱动的功能验证,分析,纠错流程,并支持验证环境的自动生成。
  • Packaging:--
  • Category:System Design and Verification



When digital simulation became common-place in the 1980s, flows were simple: RTL, then gate, then implement. In the intervening years, simulation has matured into verification and become the critical means to enable productivity, predictability, and quality in modern, complex FPGAs, ASICs, and custom designs. As part of that maturation, new means for generating metrics to measure the progress against the verification plan, new abstractions for both digital and analog simulation moving verification earlier in the process, and new means for speeding convergence have emerged. IES continues to lead these changes in the verification process by adding new technology to support each of these new niches that have emerged making IES the most used engine in the industry.

Today, the Cadence® Incisive® Enterprise Simulator fuels testbench automation, reuse, and analysis to verify designs from the system level, through RTL, to the gate level. It supports the metric-driven approach implemented by the Incisive Enterprise Manager. Its native-compiled architecture speeds the simultaneous simulation of transaction-level, behavioral, low-power, RTL, and gate-level models, eliminating the performance degradation often seen in other simulation approaches.

Incisive Enterprise Simulator also supports all IEEE-standard languages, the (OVM), the emerging Accellera Universal Verification Methodology (UVM), and the e Reuse Methodology (eRM), so engineers can quickly and easily integrate it with established verification flows. Verification engineers can extend the functionality of Enterprise Simulator with , which provide a high-throughput channel between the testbench and the device under test (DUT), and enable automated metric driven verification of embedded software exactly as if it were another part of the DUT.

Benefits
  • Fuels testbench automation, analysis, and reuse for increased productivity
  • Ensures verification quality by tracking industry-standard coverage metrics, including functional, transactional, low-power, and HDL code, plus automatic data and assertion checking
  • Drives and guides verification with an automatically backannotated and executable verification plan
  • Creates reusable sequences and multi-channel virtual sequences on top of a multi-language verification environment
  • Configures existing Universal Verification Components (UVCs) or quickly constructs all-new UVCs
  • Enables advanced debug using SimVision for transaction-level models, SystemVerilog/e class libraries, transient mixed-signal, low-power, and traditional waveform analysis
  • Supports e, Open Verification Library (OVL), OVM class library, emerging UVM class library, SystemC®, SystemC Verification Library, SystemVerilog, Verilog®, VHDL, PSL, SVA, and CPF
  • Delivers the highest possible performance for mixed-language, mixed-signal, and low-power designs, across multiple levels of abstraction, including the ability to “hot swap” the RTL simulation in/out of the Palladium XP series of accelerators/emulators

Conference Paper
No. PDF Description
1 Apples versus Apples HVL Comparison Finally Arrives Conference Paper Presented at DVCon 2010 Apples versus Apples HVL Comparison Finally Arrives Conference Paper Presented at DVCon 2010
2 Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodol Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodology
3 Coverage-Driven AMS Verification of a 4Mb Z-RAM Macro Coverage-Driven AMS Verification of a 4Mb Z-RAM Macro
4 Developing a Gigabit Ethernet VIP Using The Plan-to-Closure Methodology Featuring SystemVerilog Developing a Gigabit Ethernet VIP Using The Plan-to-Closure Methodology Featuring SystemVerilog
5 Functional Closure using the Plan-to-Closure Methodology Functional Closure using the Plan-to-Closure Methodology
6 Implementing an Automated Checking Scheme for a Video-Processing Device Implementing an Automated Checking Scheme for a Video-Processing Device
7 Integrating Design IP and Verification IP to Ensure Quality and Predictability Integrating Design IP and Verification IP to Ensure Quality and Predictability
8 Mixed Signal Verification of Dynamic Adaptive Power Conference Paper Presented at DVCon 2010 Mixed Signal Verification of Dynamic Adaptive Power Conference Paper Presented at DVCon 2010
9 Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog
10 Plan-to-Silicon: Functional Test Automation using the Incisive Platform and Plan-to-Closure Methodol Plan-to-Silicon: Functional Test Automation using the Incisive Platform and Plan-to-Closure Methodology
11 Verification Test Sequence Reuse from Block to System within Incisive Plan-to-Closure Methodology Verification Test Sequence Reuse from Block to System within Incisive Plan-to-Closure Methodology
12 Where OOP Falls Short of Hardware Verification Needs Conference Paper Presented at DVCon 2010 Where OOP Falls Short of Hardware Verification Needs Conference Paper Presented at DVCon 2010
Success Story
No. PDF Description
1 Cadence and LSI Corporation Success Story Cadence and LSI Corporation Success Story
2 Cadence and Siemens Sucess Story Cadence and Siemens Sucess Story
3 Cadence and Silicon Laboratories Cadence and Silicon Laboratories
4 Cadence and Xilinx Success Story Cadence and Xilinx Success Story
Datasheet
No. PDF Description
1 Cadence Export Model Packager Datasheet Cadence Export Model Packager Datasheet
2 Incisive Enterprise Simulator Datasheet Incisive Enterprise Simulator Datasheet
Technical Paper
No. PDF Description
1 Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf
2 Hardware Simulator Performance Scaling to Meet Advanced Node SoC Verification Requirements Technical Hardware Simulator Performance Scaling to Meet Advanced Node SoC Verification Requirements Technical Paper
White Paper
No. PDF Description
1 Enterprise System-Level (ESL) Verification Solution Beyond "First Silicon Success" White Paper Enterprise System-Level (ESL) Verification Solution Beyond "First Silicon Success" White Paper
2 Metric-Driven Verification Ensures Software Development Quality White Paper Metric-Driven Verification Ensures Software Development Quality White Paper
3 Power-Aware Verification Spans IC Design Cycle White Paper Power-Aware Verification Spans IC Design Cycle White Paper
Release Information
No. PDF Description
1 Interview: By Popular Demand—SystemVerilog Open Verification Methodology Interview: By Popular Demand—SystemVerilog Open Verification Methodology
Cadence Article
No. PDF Description
1 Interview: Closing in on Profitability with Leading-Edge Verification Practices Interview: Closing in on Profitability with Leading-Edge Verification Practices
2 Interview: Verification Planning and Management Methodology Focuses on All the Right Things Interview: Verification Planning and Management Methodology Focuses on All the Right Things
Application Brief
No. PDF Description
1 Modeling for Stimulus Generation, EZ-start Guide Modeling for Stimulus Generation, EZ-start Guide
eBook
No. PDF Description
1 Practical Guide to Low-Power Design - User Experience with CPF Practical Guide to Low-Power Design - User Experience with CPF
Contact Us

Contact Us

Telephone
+86 400 8830 393

Fax
+86(755) 2674 4090

E-mail
service_info@cogobuy.com

WeChat
芯云<cogocloud>

Quick RFQ
Quick RFQ
Buying Guide
Buying Guide
cogocloud

cogocloud

cogocloud
Go to Top