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Incisive Software Extensions

Incisive Software Extensions

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:通过指标为导向的技术来提供高效的,高质量的,可预测性优势,用于软/硬件协同验证,统一的软/硬件调试和嵌入式软件跟踪技术。充分利用和扩展了现有的Incisive验证环境,并支持软件运行在任何一种处理器上。
  • 封装:--
  • 类别:系统设计与验证



Cadence® Incisive® Software Extensions performs advanced functional verification using the Universal Verification Methodology and provides a unified hardware/software debug environment in the SimVision debugger. By applying advanced functional verification the overall software and system quality can be improved, hardware/software integration schedules shortened, and resource costs reduced.

Features/Benefits
  • Unified hardware and software debug windows in a single GUI
  • Universal Verification Methodology testbenches make function calls, check parameter results, and measure coverage for embedded software and hardware
  • Supports processor models in any form (workstation-based host-code execution, Instruction Set Simulators (ISS), RTL models, hardware acceleration and emulation, and prototype silicon)
  • Supports design models in RTL or SystemC simulation, RTL acceleration, or silicon
  • More efficient verification closure using the vPlan and Metric Driven Verification of hardware/software

Conference Paper
序号 PDF 描述
1 Coverage-Driven AMS Verification of a 4Mb Z-RAM Macro Coverage-Driven AMS Verification of a 4Mb Z-RAM Macro
2 Developing a Gigabit Ethernet VIP Using The Plan-to-Closure Methodology Featuring SystemVerilog Developing a Gigabit Ethernet VIP Using The Plan-to-Closure Methodology Featuring SystemVerilog
3 Functional Closure using the Plan-to-Closure Methodology Functional Closure using the Plan-to-Closure Methodology
4 Implementing an Automated Checking Scheme for a Video-Processing Device Implementing an Automated Checking Scheme for a Video-Processing Device
5 Integrating Design IP and Verification IP to Ensure Quality and Predictability Integrating Design IP and Verification IP to Ensure Quality and Predictability
6 Mixed Signal Verification of Dynamic Adaptive Power Conference Paper Presented at DVCon 2010 Mixed Signal Verification of Dynamic Adaptive Power Conference Paper Presented at DVCon 2010
7 Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog
8 Plan-to-Silicon: Functional Test Automation using the Incisive Platform and Plan-to-Closure Methodol Plan-to-Silicon: Functional Test Automation using the Incisive Platform and Plan-to-Closure Methodology
9 Verification Test Sequence Reuse from Block to System within Incisive Plan-to-Closure Methodology Verification Test Sequence Reuse from Block to System within Incisive Plan-to-Closure Methodology
10 Where OOP Falls Short of Hardware Verification Needs Conference Paper Presented at DVCon 2010 Where OOP Falls Short of Hardware Verification Needs Conference Paper Presented at DVCon 2010
11 Apples versus Apples HVL Comparison Finally Arrives Conference Paper Presented at DVCon 2010 Apples versus Apples HVL Comparison Finally Arrives Conference Paper Presented at DVCon 2010
12 Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodol Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodology
Technical Paper
序号 PDF 描述
1 Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf
White Paper
序号 PDF 描述
1 Enterprise System-Level (ESL) Verification Solution Beyond "First Silicon Success" White Paper Enterprise System-Level (ESL) Verification Solution Beyond "First Silicon Success" White Paper
2 Metric-Driven Verification Ensures Software Development Quality White Paper Metric-Driven Verification Ensures Software Development Quality White Paper
3 Power-Aware Verification Spans IC Design Cycle White Paper Power-Aware Verification Spans IC Design Cycle White Paper
Release Information
序号 PDF 描述
1 Interview: By Popular Demand—SystemVerilog Open Verification Methodology Interview: By Popular Demand—SystemVerilog Open Verification Methodology
Cadence Article
序号 PDF 描述
1 Interview: Closing in on Profitability with Leading-Edge Verification Practices Interview: Closing in on Profitability with Leading-Edge Verification Practices
2 Interview: Verification Planning and Management Methodology Focuses on All the Right Things Interview: Verification Planning and Management Methodology Focuses on All the Right Things
Application Brief
序号 PDF 描述
1 Modeling for Stimulus Generation, EZ-start Guide Modeling for Stimulus Generation, EZ-start Guide
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