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Palladium series

Palladium series

  • 品牌:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 经营商:科通芯城自营
  • 描述:提供业界最具扩展性,最高吞吐量,多用户加速和仿真平台。使设计人员能够快速模拟系统级设计环境,早日进入硬件/软件协同验证,并在硅流片前几个月就进行芯片确认工作。
  • 封装:--
  • 类别:系统设计与验证



The Cadence® Palladium® series delivers high system throughput, verification automation, and advanced debug to perform plan- and metric-driven system-level hardware/software co-verification. Capable of handling chip designs of up to 256 million gates, it also enables software to be developed and verified on a real hardware implementation using live data.

The Palladium series leverages advanced RTL and ESL verification automation features, such as assertion-based acceleration and transaction-based acceleration. It also uses “real-world” stimuli provided by external equipment. The Palladium series emulates HW/SW designs at up to MHz speeds— months before silicon tapeout—reducing the risk in committing to final silicon.

The Palladium series is available in I, II, and III configurations.

Features/Benefits
  • Reduces time to results with high throughput (up to 1,000,000X faster than RTL simulation)
  • Eases adoption with fast bring-up time from simulation to acceleration and emulation
  • Speeds time to closure via advanced interactive runtime debug with dynamic probes and events, FullVision and Infinite Trace
  • Teams with “real-world” external test equipment and systems via plug-n-play SpeedBridge® adapters for standard bus protocols
  • Leverages Incisive Enterprise Manager to manage verification system-wide
  • Supports industry standard languages:
    - Testbench development: Verilog®, SystemVerilog, C, C++, SystemC® Verification Library, and e
    - Assertion-based acceleration: OVL, PSL, SVA, and the Incisive Assertion Library
    - Transaction-based acceleration: SystemC, C, C++, and e models
    - Assertion-based verification IP: AHB, AXI, Gigabit Ethernet (GMII), USB 2.0

White Paper
序号 PDF 描述
1 Building Energy-Efficient ICs from the Ground Up White Paper Building Energy-Efficient ICs from the Ground Up White Paper
2 De-Mystifying SCE-MI Transactors for Simulation Acceleration White Paper De-Mystifying SCE-MI Transactors for Simulation Acceleration White Paper
3 Integrating Virtual Prototypes with IC Verification White Paper Integrating Virtual Prototypes with IC Verification White Paper
4 Power-Aware Verification Spans IC Design Cycle White Paper Power-Aware Verification Spans IC Design Cycle White Paper
Success Story
序号 PDF 描述
1 Cadence and Agere Success Story Cadence and Agere Success Story
2 Cadence and Sigma Success Story Cadence and Sigma Success Story
3 Cadence and STMicroelectronics Success Story Cadence and STMicroelectronics Success Story
4 Cadence and Unisys Success Story Cadence and Unisys Success Story
Datasheet
序号 PDF 描述
1 Cadence Palladium Series with Incisive XE Software Datasheet Cadence Palladium Series with Incisive XE Software Datasheet
2 Cadence SpeedBridge adapter for ARM Logic Tiles Datasheet Cadence SpeedBridge adapter for ARM Logic Tiles Datasheet
3 Cadence SpeedBridge Adapter for Multi-ethernet Datasheet Cadence SpeedBridge Adapter for Multi-ethernet Datasheet
Conference Paper
序号 PDF 描述
1 HW/SW Co-Simulation HW/SW Co-Simulation
2 Network Processor HW/SW Co-Verification: A Case Study Network Processor HW/SW Co-Verification: A Case Study
3 Next-Generation SoC Architectures Will Include Intrinsic Ability to See Inside Silicon Next-Generation SoC Architectures Will Include Intrinsic Ability to See Inside Silicon
4 Specman Technology and Palladium System Speed up Time to Market While Reducing Risk of Respins Specman Technology and Palladium System Speed up Time to Market While Reducing Risk of Respins
5 Speeding up HW/SW Co-Development using HW Emulation Speeding up HW/SW Co-Development using HW Emulation
Cadence Article
序号 PDF 描述
1 QLogic Depends on Verification for First-time Silicon Success QLogic Depends on Verification for First-time Silicon Success
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