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Allegro PCB SI

Allegro PCB SI

  • 卖家:Cadence
  • 包装:--
  • 无铅情况/ROHS: --
  • 描述:Provides advanced interconnect modeling for constraint development and electrical analysis of multi-gigabit designs. Simulates high-speed signals, systems, and power delivery networks at the single- or multi-board level.
  • 封装:--
  • 类别:Allegro PCB



Integrated with Cadence® Allegro® PCB design, editing, and routing technologies, Allegro PCB SI provides advanced signal integrity (SI) analysis both pre- and post-layout. Operating early in the design cycle allows for “what-if” scenario exploration, sets more accurate design constraints, and reduces design iterations.

Allegro PCB SI reads and writes directly to the Allegro PCB Editor database for fast and accurate integration of results. It provides a SPICE-based simulator and an embedded field solver, and it supports behavioral modeling with a robust modeling language. Bus architecture can be explored pre-layout to compare alternatives, or post-layout for a comprehensive analysis of all associated signals. The Allegro PCB Power Delivery Network (PDN) Analysis Option provides modeling of all power distribution characteristics.

Features/Benefits
  • Performs a wide variety of SI analyses
  • Reduces design errors to increase first-pass success
  • Sets accurate constraints, quickly and early in the process
  • Improves product performance through solution-space exploration
  • Explores alternative topologies in the earliest stages
  • Supports modeling and testing for multi-gigahertz signals
  • Generates S-Parameters from signal topologies
  • Generates estimated crosstalk tables to increase design efficiency
  • Performs post-layout verifications directly from Allegro PCB Editor
  • Enables device model creation, modification, and verification
  • Verifies multiple-board and silicon-package-board signal paths
  • Analyzes power distribution system characteristics

Conference Paper
序号 PDF 描述
1 2008 CDNLive MVP Case Study - New Technologies for 6 Gbps Serial Link Design and Simulation 2008 CDNLive MVP Case Study - New Technologies for 6 Gbps Serial Link Design and Simulation
2 2009 DesignCon Case Study - New Serial Link Simulation Process, 6 Gbps SAS 2009 DesignCon Case Study - New Serial Link Simulation Process, 6 Gbps SAS
3 2010 DesignCon Paper Award Finalist - Simulation Techniques for 6+ Gbps Serial Links 2010 DesignCon Paper Award Finalist - Simulation Techniques for 6+ Gbps Serial Links
4 3D S-Parameter Simulation in Allegro SI 3D S-Parameter Simulation in Allegro SI
5 A Process for Serial Link Signal Integrity Analysis - XrossTalk Magazine Article A Process for Serial Link Signal Integrity Analysis - XrossTalk Magazine Article
6 Automating FPGA-Based PC Board Designs Automating FPGA-Based PC Board Designs
7 Cadence Signal Integrity for Double Data Rate Interface Cadence Signal Integrity for Double Data Rate Interface
8 Cadence Signal Integrity for Double Data Rate Interface Cadence Signal Integrity for Double Data Rate Interface
9 How to Overcome Challenges in Designing a DDR2/DDR3 Memory System How to Overcome Challenges in Designing a DDR2/DDR3 Memory System
10 Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Links Work Right Out of the Box Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Links Work Right Out of the Box
Presentation
序号 PDF 描述
1 2008 CDNLive MVP Case Study Presentation - New Technologies for 6 Gbps Serial Link Design and Simula 2008 CDNLive MVP Case Study Presentation - New Technologies for 6 Gbps Serial Link Design and Simulation
Datasheet
序号 PDF 描述
1 Allegro PCB Power Delivery Network Analysis Datasheet Allegro PCB Power Delivery Network Analysis Datasheet
2 Cadence OrCAD PCB SI Datasheet Cadence OrCAD PCB SI Datasheet
3 Cadence PCB Signal and Power Integrity Datasheet Cadence PCB Signal and Power Integrity Datasheet
Cadence Article
序号 PDF 描述
1 Interview: Signals on Serial Links: Now you see ‘em, now you don’t. What can we do? Interview: Signals on Serial Links: Now you see ‘em, now you don’t. What can we do?
White Paper
序号 PDF 描述
1 IR-Drop Analysis White Paper IR-Drop Analysis White Paper
Technical Paper
序号 PDF 描述
1 Memory Design Considerations when Migrating to DDR3 Interfaces from DDR2 Memory Design Considerations when Migrating to DDR3 Interfaces from DDR2
Application Note
序号 PDF 描述
1 Modeling Analog Circuits with Routed Interconnect using AMS and Allegro SI Modeling Analog Circuits with Routed Interconnect using AMS and Allegro SI
2 Using mm.pl to Create DML MacroModels for Use in Channel Analysis Using mm.pl to Create DML MacroModels for Use in Channel Analysis
Downloads
序号 PDF 描述
1 Xilinx RocketIO Design Kit Xilinx RocketIO Design Kit
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